The present invention relates to a filter circuit applicable to a matched filter for a spread spectrum communication system.
A matched filter judges whether two signals are the same. In a spread spectrum communication system, such as mobile cellular radio or wireless local area network (LAN), each user processes a received signal by the matched filter having a spreading code allocated. A correlation peak is detected from the output of the matched filter so that synchronization, acquisition and holding are performed.
When the spreading code is PN(i), chip time is Tc, spreading ratio is M, and an input signal and correlation output are S(t) and R(t) at a time t, the following formula (1) is given.                               R          ⁡                      (            t            )                          =                              ∑                          i              =              0                                      M              -              1                                ⁢                                    PN              ⁡                              (                i                )                                      ·                          S              ⁡                              (                                  t                  -                                      i                    ·                    Tc                                                  )                                                                        (        1        )            
Here, PN(i) is a sequence of one bit data.
Double sampling or higher order over sampling is necessary for acquisition, so a plurality of matched filters are needed. The calculation of formula (1) is performed in a plurality of matched filters simultaneously, and one of the calculation results is selectively output or a plurality of outputs are added. The matched filter is constructed by a digital circuit or a surface acoustic wave (SAW) device. The former has large circuit size and consumes a lot of electrical power. Therefore it is inadequate for a mobile phone. The latter has a low S/N ratio and it is difficult to incorporate it with other circuits within one large scale integrated circuit (LSI).
The inventors of the present invention have considered the filter circuits above based on an analog calculation circuit. The analog calculation circuit has an inverting amplifier, and input capacitance connected to an input of the amplifier and a feedback capacitance connected between the input and an output of the amplifier. A sampling and holding circuit, adder, multiplication circuit, integration circuit and other circuits of high speed, low power and high accuracy circuits are realized.
FIG. 18(a) shows an example of such an analog calculation circuit. V1 and V2 are input terminals, Vo is an output terminal and INV is an inverting amplifier. The inverting amplifier INV consists of CMOS inverters working in an area of transition of output from high level to low level or from low level to high level. An odd number of CMOS inverters, shown as three stages of CMOS inverters 201, 202 and 203 in the figure, are serially connected. A serial circuit of resistance R and a capacitance C is connected between an input and output of the CMOS inverter 202. This serial circuit works as a negative feedback circuit as well as a load of the CMOS 202 for decreasing the gain of the inverting amplifier INV. A capacitance Cg is connected to the inverting amplifier INV for phase compensation so that unexpected oscillation is prevented.
Input capacitances C1 and C2 are connected between a point B at the input of INV and the input terminal V1, and between the point B and V2, respectively. A feedback capacitance Cf is connected between the output terminal Vo and the point B.
The gain of the inverting amplifier is very high, so the voltage at the point B is a constant value Vb. The point B is connected to the gate of the transistors of the CMOS inverter 201 and is a floating point or insulated point from any electrical source.
Assuming that the electrical charge of the capacitances is zero at the initial condition, the total charge at point B is zero after voltages V1 and V2 are input. Thus resulting in the following formula (2) of xe2x80x9cpreservation of electrical chargexe2x80x9d.
C1(V1xe2x88x92Vb)=C2(V2xe2x88x92Vb)+Cf(V0xe2x88x92Vb)=0xe2x80x83xe2x80x83(2)
When V1 and V2 are voltages from the voltage Vb with point B as a reference point, and defining V(1)=V1xe2x88x92Vb, V(2)=+V2xe2x88x92Vb and Vout=Voxe2x88x92Vb provides formula (3) which is obtained from the formula (2).                     Vout        =                  -                      (                                                                                C                    1                                    Cf                                ⁢                                  V                  ⁡                                      (                    1                    )                                                              +                                                                    C                    2                                    Cf                                ⁢                                  V                  ⁡                                      (                    2                    )                                                                        )                                              (        3        )            
A voltage Vout is output as an inverted voltage of a summation of input voltages V(i) (i=1,2) multiplied by a coefficient (Ci/Cf), a ratio of the input capacitance Ci and the feedback capacitance Cf.
The voltage Vb at the point B is usually Vdd/2 for maximizing the dynamic range. This voltage is called Vref, hereinafter. and Vref=+Vb=Vdd/2.
If C1=C2=Cf, the output voltage Vout=xe2x88x92{V(1)+V(2)}. A summation of both input voltages is thus obtained and, an adder is realized.
As shown in FIG. 18(b), a similar relationship to the above is applicable when more input voltages are input. Then, the formula (4) is obtained.                     Vout        =                  -                      (                                                                                C                    1                                    Cf                                ⁢                                  V                  ⁡                                      (                    1                    )                                                              +                                                                    C                    2                                    Cf                                ⁢                                  V                  ⁡                                      (                    2                    )                                                              +              …              +                                                                    C                    i                                    Cf                                ⁢                                  V                  ⁡                                      (                    i                    )                                                              +              …              +                                                                    C                    n                                    Cf                                ⁢                                  V                  ⁡                                      (                    n                    )                                                                        )                                              (        4        )            
If the input capacitances Ci (i=1 to n) are equal to Cf, that is, Ci=Cf (i=1 to n), an output voltage is obtained as a summation of input voltages. An adder of a plurality of inputs is realized.
A sampling and holding circuit using the above analog circuit is shown in FIG. 19. Vin is an input voltage, SW is a sampling switch, Cin is an input capacitance connected to the input of the inverting amplifier INV, Cf is a feedback capacitance and Vout is an output voltage. The input capacitance and the feedback capacitance have equal values. The sampling switch SW is for example a switching circuit consisting of a MOS transistor such as CMOS transmission gate.
The sampling and holding circuit corresponds to a circuit shown in FIG. 18(a) wherein the number of inputs is reduced to one. Since Cin and Cf are equal to each other, Vout=xe2x88x92Vin. At first the sampling switch SW is closed so as to sample the input signal. When SW is opened, an inverted voltage of the input voltage at the time is output from the ouput terminal The voltage is held until the sampling switch SW is closed. Accordingly, a sampling and holding circuit is realized.
An analog digital multiplication circuit using the above analog calculation circuit is shown in FIG. 20. Vin is an input voltage, Vref is the reference voltage and Vref=Vdd/2=Vb. MUX1 to MUXn are multi-plexers for switching capacitances having the first input terminals connected to V1, the second input terminals connected to Vref and output terminal connected to C1 to Cn, respectively. Control signals d1 to dn are input to the multi-plexers MUX1 to MUXn, respectively. Vin is selected to be input to C1 when di (i=1 to n) is xe2x80x9c1xe2x80x9d, and Vref is selected when di (i=1 to n) is xe2x80x9c0xe2x80x9d.
The capacitances C1 to Cn have capacity ratios that are powers of xe2x80x9c2xe2x80x9d, as defined by formula (5)
CN=2CNxe2x88x921= . . . =2xe2x80x2CHxe2x88x92i= . . . =2nxe2x88x921 C1xe2x80x83xe2x80x83(5)
The formula for holding electrical charge is defined by equation (6).                                                         ∑                              i                =                1                            n                        ⁢                                          C                i                            ⁢                                                d                  i                                ⁡                                  (                                                            V                      IN                                        -                    Vb                                    )                                                              +                                    ∑                              i                =                1                            n                        ⁢                                                            C                  i                                ⁡                                  (                                      1                    -                                          d                      i                                                        )                                            ⁢                              (                                                      V                    ref                                    -                  Vb                                )                                              +                      Cf            ⁡                          (                              Vout                -                Vb                            )                                      =        0                            (        6        )            
The output voltage Vout is defined by formula (7), wherein Vref=Vb.                     Vout        =                                            -                              xe2x80x83                            ⁢                              1                Cf                                      ⁢                                          ∑                                  i                  -                  1                                n                            ⁢                                                C                  i                                ⁢                                  d                  i                                ⁢                                  V                                      i                    ⁢                                          xe2x80x83                                        ⁢                    n                                                                                =                                                    C                1                            Cf                        ⁢                          V                              i                ⁢                                  xe2x80x83                                ⁢                n                                      ⁢                                          ∑                                  i                  -                  1                                n                            ⁢                                                2                                      n                    -                    i                                                  ⁢                                  d                  i                                                                                        (        7        )            
Vin multiplied by a binary number on n-bits corresponding to d1 to dn is obtained as Vout. Therefore, a multiplication circuit for multiplying an analog data by a digital data is realized.
Various analog calculation circuits can be constructed by the above analog calculation circuit. The analog calculation circuit is a voltage driven type, so the electrical power consumption is very low. The circuit is easy to incorporate within an LSI. Various circuits other than the filter circuit (ADF: analog digital filter) can be realized using the sampling and holding circuit, multiplication circuit and adder above.
The above analog calculation circuit has a calculation error due to an error of the capacity ratio (inclination) caused by parasitic capacitance of wiring and manufacturing deviation of capacitances. In mass-production, it is difficult to correct the error by additional resistance or additional capacitance because each LSI may have differing errors from others and adjacent circuits within one LSI may have different errors.
The present invention has an object to provide a filter circuit of smaller circuit size and lower power consumption than the conventional filter.
The present invention has another object to provide a filter circuit of higher accuracy than the conventional circuit.
According to the present invention, an analog calculation circuit in a filter circuit corrects the calculation error by estimating the error from a calculation result of known inputs and a known multiplier. A multiplier is changed according to the estimated error.
According to the present invention, a filter circuit has a voltage to current converter at an input side and a current to voltage converter at an output side and a calculation of current is performed therein.